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| 1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. 40v precision instrumentation amplifier with differential adc driver ISL28617 the ISL28617 is a high performance, differential input, differential output instrumentation amplifier de signed for precision analog to digital applications. it can operate over a supply range of 8v (4v) to 40v (20v) and features a differential input voltage range up to 34v. the output stage has rail-to-rail output drive capability optimized for differential adc driver applications. its versatility and small package makes it suitable for a variety of general purpose applications. additional features not found in othe r instrumentation amplifiers enable high levels of dc precision and excellent ac performance. the gain of the ISL28617 can be programmed from 0.1 to 10,000 via two external resistors, r in and r fb . the gain accuracy is determined by the matching of r in and r fb . the gain resistors have kelvin sensing, which removes gain error due to pc trace resistance. the input and output stages have individual power supply pins, which enable input signals riding on a high common mode voltage to be level shifted to a low voltage device, such as an a/d converter. the rail-to-rail output stage can be powered from the same supplies as the adc, which preserves the adc maximum input dynamic range and eliminates adc input overdrive. the ISL28617 is offered in the 24 ld tssop package, and is guaranteed over -40c to +125c operation. related literature ? ?ISL28617vyxxev1z user?s guide? an1753 ? ?ISL28617smxxev1z user?s guide? an1748 features ? rail-to-rail differential output adc driver ? high voltage interface to low voltage circuits ? wide operating voltage range . . . . . . . . . . . . . . 4v to 20v ? low input offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 v ? excellent cmrr and psrr . . . . . . . . . . . . . . . . . . . . . . . 120db ? closed loop -3db bw . .0.3mhz (a v = 1k) to 5mhz (a v =0.1) ? operating temperature range. . . . . . . . . . .-40c to +125c ? package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ld tssop applications ? precision test and measurement ? high voltage industrial process control ? signal conditioning amplifier for remote powered sensors ?weigh scales ? ecg and biomedical sense amplifiers figure 1. cmrr r f = 121k r in +r in -r in in+ +r in sense -r in sense in- +r fb -r fb +r fb sense -r fb sense v cc v co gnd v ee v eo r fb +v out -v out v cmo v ref +5v +5v to +20v -5v to -20v ISL28617 a-d r c bridge v dd gnd r -v fb +v fb converter excitation full bridge strain gauge amplifier and differential adc driver +in -in isl26132 v ref isl21090 av = r fb /r in range from 0.1 to 10,000 figure 2. basic application circuit 0 20 40 60 80 100 120 140 c m r r ( db ) frequency(hz) 1 10 100 1k 10k 100k 1m a v = 0.1 a v = 100 a v = 1000 a v = 10 a v = 1 may 25, 2012 fn6562.0
ISL28617 2 fn6562.0 may 25, 2012 sl28617 (24 ld tssop) top view 1 2 3 4 24 23 22 21 5 6 7 20 19 18 8 17 nc dnc +r fb in+ in- dnc +r in +r fb sense +r in sense -r fb sense -r fb -r in sense -r in gnd v cmo 9 10 11 16 15 14 12 13 v cc v ee v co +v fb v eo -v fb +v out -v out dnc pin descriptions pin name pin numbers description nc 1 no internal connection dnc 2, 3, 22 for internal use; do not connect +r fb 4 feedback resistor, r fb + pin +r fb sense 5 +r fb , positive sense pin connects to the resistor r fb + terminal to form the r fb + kelvin connection -r fb sense 6 -r fb , negative sense pin connects to the resistor r fb - terminal to form the r fb - kelvin connection -r fb 7 feedback resistor, negative terminal gnd 8 ground pin is capacitively coupled to the internal esd circuit and should be connected to power supply common or signal gnd. v cc 9 positive supply for input stage and feedback amp v co 10 positive supply for output stage +v fb 11 positive output feedback +v out 12 positive output -v out 13 negative output -v fb 14 negative output feedback v eo 15 negative supply for output stage v ee 16 negative supply for input stage and feedback amp v cmo 17 output common mode reference input -r in 18 input resistor, negative terminal -r in sense 19 -r in , negative sense pin connects to the resistor r in - terminal to form the r in - kelvin connection +r in sense 20 +r in , positive sense pin connects to the resistor r in + terminal to form the r in + kelvin connection +r in 21 input resistor, positive terminal in- 23 negative input in+ 24 positive input ordering information part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # ISL28617fvz 28617 fvz -40c to +125c 24 ld tssop m24.173 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL28617 . for more information on msl please see tech brief tb363 . ISL28617 3 fn6562.0 may 25, 2012 simplified block diagram +15v +r in -r in gnd in+ in- r in -15v in+ +out -out v cmo +r in sense -r in sense v ee v eo v cc +v out -v out in- ISL28617 v co gnd r l +r fb -r fb r fb +v fb +r fb sense -r fb sense -v fb v cc v cc v ee v ee ISL28617 4 fn6562.0 may 25, 2012 important note: all parameters having min/max specifications ar e guaranteed. typ values are for information purposes only. unle ss otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maximum rating s thermal information maximum supply voltage (v cc to v ee or gnd) . . . . . . . . . . . . . . . . . . . . 42v maximum supply voltage (v co to v eo or gnd) . . . . . . . . . . . . . . . . . . . . 42v maximum voltage (v co to v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.5v, -40v maximum voltage (v eo to v-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v, +40v maximum differential input current . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma max/min input current for input voltage >v cc or ISL28617 6 fn6562.0 may 25, 2012 i n input noise current de nsity f = 1khz 150 fa/ hz i n ierr total internal noise cu rrent density f = 1khz 2.6 pa/ hz i n ierr rms 0.1 to 10hz total internal rms noise current f = 0.1 to 10hz 4 parms -3db bw -3db bandwidth vs. closed loop gain, r fb = 30.1k r fb = 30.1k ; r in = 301k ; g = 0.1 5.5 mhz r fb = 30.1k ; r in = 30.1k ; g = 1 2.6 mhz r fb = 30.1k ; r in = 3.01k ; g = 10 2.2 mhz r fb = 30.1k ; r in = 301 ; g = 100 2.0 mhz r fb = 30.1k ; r in = 30.1 ; g = 1000 0.3 mhz -3db bw -3db bandwidth vs. closed loop gain, r fb = 121k r fb = 121k ; r in = 1.21m ; g = 0.1 5.0 mhz r fb = 121k ; r in = 121k ; g = 1 1.4 mhz r fb = 121k ; r in = 12.1k ; g = 10 0.5 mhz r fb = 121k ; r in = 1.21k ; g = 100 0.45 mhz r fb = 121k ; r in = 121 ; g = 1000 0.4 mhz sr slew rate 4v/s t s settling time to 0.01% v out = + 2.4v, r f = 30.1k 3s v out = + 9.6v, r f = 121k 11 s notes: 5. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 6. differential gain(a v ) = r fb /r in . 7. v out , clipping ~ i rf *r fb . 8. v os,out = a v *v os,in + v os,fb + i err * r fb . 9. compliance to datasheet limits is assured by design simulation. electrical specifications v cc = v co = 15v, v ee = v eo = -15v, v cm = 0v, r l = 10k , r fb = r in = 30.1k , t a = +25c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameter description conditions min (note 5) typ max (note 5) unit ISL28617 7 fn6562.0 may 25, 2012 typical performance curves v cc = v co = 15v, v ee = v eo = -15v, v cm = 0v, r l = open, unless otherwise specified. figure 3. i err vs input common mode voltage figure 4. i err vs supply voltage (v cc - v ee ) figure 5. v osfb vs input common mode voltage figure 6. v osfb vs supply voltage (v cc - v ee ) figure 7. i os vs supply voltage (v cc - v ee ) figure 8. i os vs supply voltage (v cc - v ee ) -20 -15 -10 -5 0 5 10 15 20 -15 -10 -5 0 5 10 15 v cm (v) i e r r ( n a ) -20 -10 0 10 20 0 5 10 15 20 25 30 35 40 45 50 v sup (v cc - v ee ) i e r r ( n a ) -1000 -800 -600 -400 -200 0 200 400 600 800 1000 -15 -10 -5 0 5 10 15 v cm (v) v o s f b ( m v ) -1000 -800 -600 -400 -200 0 200 400 600 800 1000 0 5 10 15 20 25 30 35 40 45 50 v sup (v cc - v ee ) v o s f b ( m v ) -1000 -800 -600 -400 -200 0 200 400 600 800 1000 0 5 10 15 20 25 30 35 40 45 50 v sup (v cc - v ee ) i o s ( p a ) -1000 -800 -600 -400 -200 0 200 400 600 800 1000 0 5 10 15 20 25 30 35 40 45 50 v sup (v cc - v ee ) i o s ( p a ) ISL28617 8 fn6562.0 may 25, 2012 figure 9. i b vs input common mode voltage figure 10. i b vs supply voltage (v cc - v ee ) figure 11. v os in vs input common mode voltage figure 12. v os in vs supply voltage (v cc - v ee ) figure 13. ib vcmo vs v cmo input voltage range figure 14. i cc vs supply voltage (v cc - v ee ) typical performance curves v cc = v co = 15v, v ee = v eo = -15v, v cm = 0v, r l = open, unless otherwise specified. -1000 -800 -600 -400 -200 0 200 400 600 800 1000 -15 -10 -5 0 5 10 15 v cm (v) -i b +i b i b ( p a ) -1000 -800 -600 -400 -200 0 200 400 600 800 1000 0 5 10 15 20 25 30 35 40 45 50 v sup (v cc - v ee ) i b ( p a ) -i b +i b -100 -80 -60 -40 -20 0 20 40 60 80 100 -15 -10 -5 0 5 10 15 v cm (v) v o s i n ( m v ) -100 -80 -60 -40 -20 0 20 40 60 80 100 0 5 10 15 20 25 30 35 40 45 50 v sup (v cc - v ee ) v o s i n ( m v ) -5 -4 -3 -2 -1 0 1 2 3 4 5 -15 -10 -5 0 5 10 15 v cmo (v) i b v c m o ( m a ) 1 2 3 0 10 20 30 40 50 supply voltage (v cc - v ee ) supply current (ma) ISL28617 9 fn6562.0 may 25, 2012 figure 15. i co vs supply voltage ( v co - v eo ) figure 16. closed loop gain (r fb = 30.1k) vs frequency) figure 17. closed loop gain (r fb = 121k) vs frequency figure 18. positive psrr v ee & v cc (r f = 30.1k) figure 19. negative psrr v ee & v cc (r f = 30.1k) figure 20. positive psrr v ee & v cc (r f = 121k) typical performance curves v cc = v co = 15v, v ee = v eo = -15v, v cm = 0v, r l = open, unless otherwise specified. 1 2 3 0 10 20 30 40 50 supply voltage (v co - v eo ) supply current (ma) -40 -20 0 20 40 60 80 10 100 1k 10k 100k 1m 10m 100m frequency (hz) a v = 100 a v = 10 r in = 301 r fb = 30.1k a v = 1 r in = 30.1k, r fb = 30.1k gain (db) a v = 1000 r in = 30.1, r fb = 30.1k r in = 3.01k, r fb = 30.1k r in = 301k, r fb = 30.1k a v = 0.1 -40 -20 0 20 40 60 80 frequency (hz) 10 100 1k 10k 100k 1m 10m 100m a v = 100 a v = 1000 a v = 10 r fb = 121k a v = 1 gain (db) a v = 0.1 r in = 12.1k, r fb = 121k r in = 121k, r fb = 121k r in = 1.21k r in = 121, r fb = 121k r in = 1.21m, r fb = 121k 0 20 40 60 80 100 120 140 160 1 10 100 1k 10k 100k 1m p o s i t i v e p s r r ( d b ) frequency (hz) a v = 0.1 a v = 100 a v = 1000 a v = 10 a v = 1 0 20 40 60 80 100 120 140 160 n e g a t i v e p s r r ( d b ) frequency (hz) 1 10 100 1k 10k 100k 1m a v = 0.1 a v = 100 a v = 1000 a v = 10 a v = 1 0 20 40 60 80 100 120 140 160 p o s i t i v e p s r r ( d b ) frequency (hz) 1 10 100 1k 10k 100k 1m a v = 0.1 a v = 100 a v = 1000 a v = 10 a v = 1 ISL28617 10 fn6562.0 may 25, 2012 figure 21. negative psrr v ee & v cc (r f = 121k) figure 22. positive psrr v e0 & v c0 (r f = 30.1k) figure 23. negative psrr v eo & v co (r f = 30.1k) figure 24. positive psrr v eo & v co (r f = 121k) figure 25. negative psrr v e0 & v co (r f = 121k) figure 26. cmrr rf = 30.1k typical performance curves v cc = v co = 15v, v ee = v eo = -15v, v cm = 0v, r l = open, unless otherwise specified. 0 20 40 60 80 100 120 140 160 n e g a t i v e p s r r ( d b ) frequency (hz) 1 10 100 1k 10k 100k 1m a v = 0.1 a v = 100 a v = 1000 a v = 10 a v = 1 0 20 40 60 80 100 120 140 160 180 frequency (hz) 1 10 100 1k 10k 100k 1m p o s i t i v e p s r r ( d b ) a v = 0.1 a v = 100 a v = 1000 a v = 10 a v = 1 0 20 40 60 80 100 120 140 160 180 n e g a t i v e p s r r ( d b ) frequency (hz) 1 10 100 1k 10k 100k 1m a v = 0.1 a v = 100 a v = 1000 a v = 10 a v = 1 0 20 40 60 80 100 120 140 160 180 200 p o s i t i v e p s r r ( d b ) frequency (hz) 1 10 100 1k 10k 100k 1m a v = 0.1 a v = 100 a v = 1000 a v = 10 a v = 1 0 20 40 60 80 100 120 140 160 n e g a t i v e p s r r ( d b ) frequency (hz) 1 10 100 1k 10k 100k 1m a v = 0.1 a v = 100 a v = 1000 a v = 10 a v = 1 0 20 40 60 80 100 120 140 c m r r r f b = 3 0 . 1 k ( d b ) frequency (hz) 1 10 100 1k 10k 100k 1m a v = 0.1 a v = 100 a v = 1000 a v = 10 a v = 1 ISL28617 11 fn6562.0 may 25, 2012 figure 27. cmrr r f = 121k figure 28. input voltage and current noise typical performance curves v cc = v co = 15v, v ee = v eo = -15v, v cm = 0v, r l = open, unless otherwise specified. 0 20 40 60 80 100 120 140 c m r r r f b = 1 2 1k ( d b ) frequency (hz) 1 10 100 1k 10k 100k 1m a v = 0.1 a v = 100 a v = 1000 a v = 10 a v = 1 1pa 1nv 10nv 1000nv 0.1 1 10 100 1k 10k 100k frequency (hz) 100nv 0.1pa 0.01pa input noise voltage (v/ hz) e n i n figure 29. ISL28617 functional block diagram in+ r in in- r fb 100a + - v cmo v fb- -v out + - + - + - v cc v ee v eo v co v fb+ +v out 100a input feedback output stage stage stage +r in sense -r in sense a1 a2 a3 a4 -r fb sense +r fb sense q1 q2 q3 q4 i1 i2 i3 i4 0.1f 0.1f 0.1f 0.1f gnd gain resistors and kelvin connections 500 ? 500 ? a5 +r in -r in +r fb -r fb i s1 i s2 i s3 i s4 i1, i3 i2, i4 + - a6 ISL28617 12 fn6562.0 may 25, 2012 applications information section 1 contains the ISL28617 functional and performance objectives and description of operation. section 2 contains the applicatio n circuit design equations and guidelines for achieving the desired dc and ac performance levels. section 3 provides equations for predicting dc offset voltage and noise of the finished design. 1. general description the ISL28617 instrumentation amplifier was developed to accomplish the following: ? provide a fully differential, rail-to-rail output for optimally driving adcs. ? limit the output swing to prevent output overdrive. ? allow any gain, including attenuation. ? maximize gain accuracy by removing on-chip component tolerances and external pc board parasitic resistance. ? enable user control of amplifier precision level with choice of external resistor tolerance. ? maintain cmrr>100db and remove cmrr sensitivity to gain resistor tolerance. ? provide a level shift interface fr om bipolar analog input signal sources to unipolar, and bipolar adc output terminations. functional description (figure 29) figure 29 shows the functional block diagram for the ISL28617. input g m amplifier the input stage consists of high performance, wide band amplifiers a1, a2, g m drive transistors q1, q2, and input gain resistor r in . current drive for q1 and q2 emitters are provided by matched pair of 100a current sinks. a unity gain buffer from each input (in+, in-) to the terminals of the input resistor, r in , is formed by the connection of the kelvin resistor sense pins and drive pins to the terminals of the input resistor, as shown in figure 29. in this configuratio n, the voltage across the input resistor r in is equal to the input differential voltage across in+ and in-. the input g m stage operates by creating a current difference in the collector currents q1 and q2 in response to the voltage difference between the in+ and in- pins. when the input voltage applied to the in+ and in- pins is zero, the voltage across the terminals of the gain resistor r in , is also zero. since there is no current flow through the gain resistor, the transistors q1, and q2 collector currents i1, i2 are equal. a change in the input differential voltage causes an equivalent voltage drop across the input gain resistor r in , and the resulting current flow through r in , causes an imbalance in q1, q2 collector currents i1, i2, given by: feedback g m amplifier the feedback amplifiers a3, a4 form a differential trans conductance amplifier identical to the input stage. the input terminals (v fb+ , v fb- ) connect to the ISL28617 differential output terminals (+v out , -v out ) so that the output voltage also appears across the feedback gain resistor r fb . operation is the same as the input g m stage and the differential currents i3, i4 are given by: error amplifier a5, output amplifier a6 (figure 29) amplifiers a5 and a6 act toge ther to form a high gain, differential i/o trans-impedance amplifier. differential current amplifier a5 sums the differential currents (i1+i3, i2+i4) from the input and feedback g m amplifiers. from that summation, a differential error voltage is sent to a6, which generates the rail- to-rail differential output drive to the +v out and -v out pins. the external connection of the output pins to the feedback amplifier closes a servo loop wher e a change in the differential input voltage is converted into differential current imbalances at i1, i2 (equations 1, 2) at the summing node inputs to a5. current i1 sums with current i3 from th e feedback stage, and i2 sums with i4. a5 senses the difference between current pairs i1, i3 and i2, i4. a difference voltage is generated, amplified and fed back to the feedback amplifier, which creates correction currents at i3, i4 to match the currents at i1, i2 (equations 3, 4). therefore, at equilibrium: combining equations 1 and 3, (a nd their complements i2 and i4), and solving for v out as a function of v in , r in and r fb , yields equation 6: equation 6 can be rearranged to form the gain equation 7: which is general form of the gain equation for the ISL28617. 2. designing with the ISL28617 to complete a working design, the following procedure is recommended and explained in this section: 1. define the output voltage swing. 2. set the feedback resistor value, r fb 3. set the input gain resistor value, r in 3. set the v co , v eo power supply voltages 4. set the v cc and v ee supply voltages (eq. 1) i 1 = 100a + (v in+ - v in- )/r in (eq. 2) i 2 = 100a - (v in+ - v in- )/r in (eq. 3) i 3 = 100a - {(+v out ) - (-v out )}/r fb (eq. 4) i 4 =100a +{(+v out ) - (-v out )}/r fb (eq. 5) i 1 = i 3 and i 2 = i 4 (eq. 6) v out = v in *r fb /r in ; where v out = (+v out ) - (-v out ) and vin = in+ - in- (eq. 7) gain = v out /v in = r fb /r in ISL28617 13 fn6562.0 may 25, 2012 the gain of the instrumentation amplifier is set by the resistor ratio r fb /r in (equation 7), and the maximum output swing is set by the absolute value of the feedback resistor r fb (equation 8). v co and v eo supply power to the rail-to-rail output stage and define the maximum output voltage swing at the v out diffrentiel output pins. power supply pins v cc and v ee power the feedback amplifiers which, require an additional 3v beyond the v co and v eo voltages to maintain linear operation of the feedback g m stage. setting the feedback gain resistor r fb (figures 29 , 30) resistor r fb defines the maximum differential voltage at output terminals +v out to -v out . external resistor r fb and the differential 100a current sources define the maximum dynamic range of the feedback stage, which defines the maximum differential output swing of the output stag e. overload circuitry allows >100a to flow through r fb to maintain feedback, but linearity is degraded. therefore, it is a good practice to keep the maximum linear dynamic range to within 80% of the maximum i*r across the resistor. in cases where large pulse overshoot is expected, the maximum current in equation 8 could be reduced to 50% for additional margin (see ?ac performance considerations? on page 15.) the penalty for increasing the feedback resistor value is higher dc offset voltage and noise. output voltages that exceed th e maximum dynamic range of the feedback amplifier can degrade phase margin and cause instability. the plot in figure 30 shows the maximum differential output voltage swing vs. resistor value for r fb and r in using the 80% and 50% current source levels. setting the input gain resistor r in (figures 29, 30) the input gain resistor r in is scaled to the feedback resistor according to the gain equation 9: the input g m stage uses the same differential current source arrangement as the feedback stage. therefore, the amount of overdrive margin (50%, 80%) included in the calculation for r fb is also included in the calculation for r in . input stage overdrive considerations (figure 31) there are a few cases where the input stage can be over driven, which must be considered in the application. an input signal that exceeds the maximum dynamic range of the gain resistor r in , calculated previously, can cause the esd diodes to conduct. when this occurs, a low impedance path from the inputs to the input gain resistor r in will result in signal distortion. high speed input signals that remain within the maximum dynamic range of the input stage can cause distortion if the input slew rate exceeds the input stage slew rate (~4v/s). when the input slews at a faster rate than the g m stage can follow, the voltage difference appears acro ss the input esd diodes from each input and resistor r in . when the voltage difference is large enough to cause the diodes to conduct, the input terminals are shunted to r in through the 500 input protection resistors, causing distortion during the rise and fall times of the transient pulse. the distortion will last until the resistor voltage catches up to the input voltage. setting the power supply voltages the ISL28617 power supplies are partitioned so that the input stage and feedback stages are powered from a separate pair of supply pins (v cc , v ee ) than the differential output stage (v co , v eo ). this partitioning provides th e user with the ability to adapt the ISL28617 to a wide variety of input signal power sources that would not be possible if the supplies were strapped together internally (v cc = v co & v ee = v eo ). however, powering the input and output supplies from unequal supplies has restrictions that are described in the next section. powering the input and feedback stages (v cc , v ee ) the input pins in+, in- cannot swing rail-to-rail, but have a maximum input voltage range given by equation 10: this requires the sum of the common mode input voltage and the differential input voltage to remain within 3v of either the v cc or v ee rail, otherwise dist ortion will result. (eq. 8) v out diff= 80a * r fb figure 30. r fb , r in vs. dynamic range 35 30 25 20 15 10 5 0 0 50 100 150 200 250 300 350 400 dynamic voltage range (v) r fb , r in value (k ? ) v out (v) @ 80% v out (v) @ 50% (eq. 9) r in = r fb /gain in+ r in in- 100a 100a + - + - v ee 500 ? v cc 500 ? esd protection esd protection figure 31. input stage esd protection diodes a1 a2 q1 q2 (eq. 10) v ee + 3v < (v cmir in + v in ) < v cc - 3v; where v in = maximum differential voltage in+ to in- ISL28617 14 fn6562.0 may 25, 2012 the feedback pins v fb + and v fb - have the same input common mode voltage constraint as the in put pins in+, in-. the maximum input voltage range of the feedback pins is given by equation 11: to maintain stability, it is critical to respect the 3v requirement in equation 11. powering the rail-to-rail output stage (v co , v eo ) the output stage (a6) is of rail -to-rail design, and is powered by the v co and v eo pins. the differential output pins +v out, -v out connect to the v fb +, v fb - pins to close the output feedback loop. the feedback stage is powered from v cc and v ee pins. the v fb +, v fb - have a common mode input range 3v below the v cc rail and 3v above the and v ee rail. if the output voltage exceeds the feedback common mode input voltage, loop instability will result. therefore, the voltages at the v out pins should always be 3v away from either rail, as shown in equation 12. rail-to-rail differential adc driver the differential output stage of the ISL28617 is designed to drive the differential input stage of an adc. in this configuration, the v co , v eo power supply pins connect directly to the adc power supply pins. this output swing arrangement is ideal for driving rail-to-rail adc drive without the possibility of over driving the adc input. the output stage is capable of rail-to-rail operation when v co , v eo are powered from a single supply or from split supplies. it has a single supply voltage range (v co ) from 3v to 15v (with v eo at gnd), and a 1.5v to 15v split su pply voltage range. under all power supply conditions, v cc must be greater than v co by 3v, and v ee must be less than v eo by 3v to maintain the rail-to-rail output drive capability. the v cmo pin is an input to a very low bias current terminal, and sets the output common mode reference voltage when driving a differential input adc, such that the output would have a input signal span centered around an external dc reference voltage applied to the v cmo pin. power supply voltages by application the ISL28617 can be adapted to a wide variety of instrumentation amplifier applicatio ns where the signal source is powered from supply voltages th at are different from the supply voltages powering downstream circuits. the following examples are included as a guide to the proper connection and voltages applied to the supply pins v cc , v ee , v co and v eo . there are a common set of requirements across all power applications: 1. a common ground connection from the input supplies, (v cc , v ee ) to the output supplies (v co , v eo ) is required for all powering options. 2. the signal input pins in+, in- cannot float, and must have a dc return path to ground. 3. the input and output supplies cannot both be operated in single supply mode due to the 3v feedback amplifier common mode headroom requirement in equation 11. the following are typical power examples: example 1: bipolar input to single supply output the ISL28617 is configured as a 5v adc driver in a high gain sensor bridge amplifier powered from a 10v excitation source. in this application, the isl286 17 must extract the low level bipolar sensor signal and shift the level to the 0v to +5v differential rail-to-rail signal needed by the adc. the following powering option is recommended: ?v cc = +10v, v ee = -10v ?v co = +5v, v eo = gnd ?v cmo = +2.5v ?v cc , v ee power supply common connects to gnd example 2: high voltage bipolar i/o buffer the ISL28617 is configured as a high impedance buffer instrumentation amplifier in a 15v industrial sensor application. in this application, the ISL28617 must extract and amplify the high impedance sensor signal and send it downstream to a differential ad c operating from 15v supplies. the following powering options are recommended: 1. input and output supplies are strapped to the same supplies and rail-to-rail input to the adc is not required. -v cc = v co = +15v -v ee = v eo = -15v -v cmo = gnd -v cc , v ee power supply common connects to gnd and v out = 12v. 2. 15v rail-to-rail output is required, then: -v cc = +18v, v ee = -18v -v co = +15v, v eo = -15v -v cmo = gnd -v cc , v ee power supply common connects to gnd the v co and v eo power supply pins connect to the adc 15v power supply pins. rail-to-rail output swing requires that v cc =v co +3v and v ee =v eo -3v, or 18v. (eq. 11) v ee + 3v < v cmir fb < v cc - 3v where v cmir fb = (+v out - -v out ) +v cmo (eq. 12) v ee + 3v < v out < v cc - 3v; where v out = | +v out | or | -v out | ISL28617 15 fn6562.0 may 25, 2012 example 3: gains less than 1 the ISL28617 is configured to a gain of 0.2v/v driving a a rail-to-rail 3v adc. in this application, the maximum input dynamic range is 15v. -v cc = +18v, v ee = -18v -v co = +3v, v eo = gnd -v cmo = +1.5v -v cc , v ee power supply common connects to gnd in this attenuator configuration, the input signal range is 15v, which requires an additional 3v of input overhead from the input supplies. thus, v cc and v ee =18v. ac performance considerations the ISL28617 closed loop frequency response is formed by the feedback g m amplifier and gain resistor r fb and has the characteristics of a current fee dback amplifier. therefore, the -3db gain does not significantly decrease at high gains as is the case with the constant gain-ban dwidth response of the classic voltage feedback amplifier. there are four behaviors of current feedback amplifiers that must be considered: ? frequency response increases with decreasing values of r fb . a comparison of the g = 100, -3db response (figures 16, 17) r fb at 30.1k vs. 121k shows almost a 4x decrease from 2mhz to 0.5mhz. ? gain peaking tends to increase with decreasing values of r fb ? wide band applications at gains less than 1 (figures 16, 17) can have high gain peaking resulting in high levels of overshoot with pulsed input signals ? parasitic capacitance at the feedback resistor terminals (+r fb , -r fb ) and the kelvin sense terminals (+r fb sense, -r fb sense) will result in increasing levels of peaking and transient response overshoot. to minimize peaking external pc parasitic capacitance should be minimized as much as possible. the ISL28617 is designed to be stable with pc board parasitic capacitance up to 20pf and feedback resistor values down to 30.1k . at gains less than 1, the maximum parasitic capacitance may have to be limited further to avoid additional compensation. uncorrected gain peaking and high overshoot in the feedback stage can cause loss of feedback loop stability if the transient causes the feedback voltage to exceed the common mode input range of the feedback amplifier or the maximum linear range of the feedback resistor r fb . corrective actions include increasing the size of the feedback resistor (see figure 30) and re-scaling the input gain resistor r in , or adding input frequency compensation described in the next section. the penalty of increasing the r fb (and r in re-scaling) is increased noise, so this is generally not the corrective action of choice ac compensation techniques input compensation with a low pass filter (figure 32) can be an effective way to block high frequency signals from the differential amplifier inputs. it does not change the gain peaking behavior of the feedback loop, but it does block signals from creating overdrive instability. this method is useful after other corrective measures have been implemented, and when there is little control over the input signal frequency content. input common mode rejection considerations the ISL28617 is capable of a very high level (120db) of cmrr performance from dc to as high as 1khz. (figure 1; cmrr vs. frequency). this high level of performance over frequency is made possible by the high co mmon mode input impedance (80g ) but requires careful attention to the matching of the in+ and in- external impedances to gnd. a mismatch in the series impedance in conjunction with parasitic capacitance at the in+, in- terminals (figure 32) will cause a common mode amplitude imbalanc e that will show up as a differential input signal, rapidly degrading cmrr as the common mode frequency increases. maximum cmrr performance is achieved with attention to balancing external components and attention to pc layout. layout guidelines the ISL28617 is a high precision device with wide band ac performance. maximizing dc prec ision requires attention to the layout of the gain resistors. achi eving good ac response requires attention to parasitic capacitance at the gain resistor terminals, and cmrr performance over frequency is ensured with symmetrical component placemen t and layout of the input differential signals to the in+ and in- terminals. to ensure the highest dc precision, the location of the gain resistors and pc trace connections to the kelvin connections are most important. proper kelvin connections remove trace resistance errors so that the am plifier gain accuracy, and gain temperature coefficients are determined by the gain resistor matching tolerance. interconnect constraints preclude mounting the gain resistors next to each other, so they should be located on either side of the ISL28617 and as close to the device as possible. the kelvin connections are formed at the junction of the sense pins ( r in sense, r fb sense) and the gain resistor current drive terminals ( r in, r fb) terminals. this junction should be made at the terminal pads directly under the ends of each resistor. in+ in- 500 ? 500 ? r/2 r/2 c gnd common mode error differential input signal figure 32. input differential low pass filter and parasitic capacitance trace capacitance ISL28617 16 fn6562.0 may 25, 2012 reduced trace lengths that maintain dc accuracy are also important for minimizi ng the capacitance that can degrade ac stability. this is especially tr ue at gains less then 1. layout techniques for precision applications using larger size precision gain resistors at very low gains (g = 0.1v/v) include removing a section of the underlying pc ground plane directly under the gain resistor terminals and body. layout guidelines for high cmrr include matching trace lengths and symmetrical component placement on the circuit that connects the signal source to the in+, in- pins. this ensures matching of the in+ and in- input impedances (figure 32). power supply de-coupling standard power supply de-coupling consists of a single 0.1f 50v ceramic capacitor at the power supply terminals located as close to the device as possible. in applications where the input and output supplies are strapped to the same voltage (v ee = v eo , v cc = v co ) the connection point should be as close to the device as possible, with a single 0.1f 50v ceramic capacitor at the junction. applications using separate supplies require 0.1f 50v ceramic de-coupling capacitors at each power supply terminal. 3. estimating amplifier dc and noise performance the gain resistor ohmic values and ratios are all that is required to estimate dc offset and noise. the following sections illustrate methods to calculate dc offset and noise performance. these estimates are useful for optimizing resistor values for noise and dc offset. calculating dc offset voltage output offset voltage, like output noise, has several contributors. also similar to output noise, the major offset contributor depends on the gain configuration. in high-gain, v os(i) dominates, while in low-gain, offset due to i err dominates. the summation of dc offsets to arrive at total dc offset error is performed in two ways. equation 13 is a simple addition of the dc offsets appearing at the output , and is useful when defining the minimum to maximum range of offset that can be expected. the drawback is that the result defines the corner of the corners of the error box, and not a typical value given that these sources are uncorrelated. equation 14 expresses the total dc error as the rms, or square root of the sum of the squares to provide an estimate of a typical value. equation 15 converts the output offset error (equation 13) range (equation 13) to an input referred error range [v os (rti)] and enables a comparison with the dc component of the input signal. similarly, equation 16 shows the typical dc offset value (equation 14) referred to the input. these results are summarized in table 1. calculating noise voltage the calculation of noise spectral density at the output [e n (rto)] from all noise sources is given by equation 17. equation 18 converts the output noise to the input referred value when evaluating the input signal to noise ratio. table 2 provides examples of the noise contribution of each source by circuit gain and output voltage span. in a high-gain configuration, the input noise is the dominant noise source. in a low-gain config uration, the noise voltage from the product of the internal noise current, i n(err) , and the feedback resistor, r fb dominates. the contribution of the internal noise current, i n(err) increases in proportion to r fb, but the corresponding increase in output voltage with r fb keeps the ratio of this noise voltage to output voltage constant. (eq. 13) v os (rto) = [(a v v os(i) ) + (v os(fb) ) + (i err r fb )] (eq. 14) v os (rto)typ = [(a v v os(i) )2+(v os(fb) )2+(i err r fb )2] (eq. 15) v os (rti) = [(v os(i) ) + (v os(fb)/ a v ) + (i err r fb ) / a v ] (eq. 16) v os (rti)typ = [v os(i) )2 + (v os(fb)/ a v )2 + (i err r fb ) / a v )2] (eq. 17) e n (rto) = [(a v e n (i))2 + (2 a v i n (i) 500 )2 + (a v )2 x (4kt r in ) + (4kt r fb ) + (r fb i n (ierr))2+(e n (fb))2] (eq. 18) e n (rti) = e n (rto)/a v table 1. computing typical output offset voltage ranges a v v o(lin) r in (k ) r fb (k ) a v x v os (i) (v) (note 10) v os (fb) (v) (note 10) i err (5na) x r fb (v) (note 10) eq. 13 v os (rto) (v) eq. 15 v os (rti) (v) eq. 14 typical v os (rto) (v) eq. 16 typical v os (rti) (v) 1 2.5 30 30 30 400 150 580 428 1 10 120 120 15 400 600 1015 721 100 2.5 0.3 30 1500 400 150 2000 20 1560 15.6 100 10 1.2 120 1500 400 600 2500 25 1669 16.7 note: 10. chosen for illustration purposes and does not reflect actual device performance. ISL28617 17 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6562.0 may 25, 2012 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: ISL28617 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php table 2. 1khz input noise and thermal noise contributions a v r in (k ) r fb (k ) a v x e n (i ) (nv/ hz) 2 x a v x i n(i) x 500 (nv/ hz) a v x (4kt x r in) (nv/ hz) (4kt x r fb) (nv/ hz) r fb x i n (i err ) (nv/ hz) e n (fb) (nv/ hz) e n (rto) output referred noise (nv/ hz) e n (rti) input referred noise (nv/ hz) 1 30 30 8.6 0.15 22.3 22.3 78 8.6 86 1 120 120 8.6 0.15 44.6 44.6 300 8.6 307 100 0.3 30 860 15 223 22.3 78 8.6 892 8.9 100 1.2 120 860 15 446 44.6 300 8.6 1015 10.15 note: 11. e n and i n values are chosen for illustration purposes and may not reflect actual device performance. revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change may 25, 2012 fn6562.0 initial release. ISL28617 18 fn6562.0 may 25, 2012 package outline drawing m24.173 24 lead thin shrink sma ll outline package (tssop) rev 1, 5/10 detail "x" typical recommended land pattern top view side view end view dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. dimensions are measured at datum plane h. dimensioning and tolerancing per asme y14.5m-1994. dimension does not include dambar protrusion. allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm. dimension in ( ) are for reference only. conforms to jedec mo-153. 6. 3. 5. 4. 2. 1. notes: 7. 5 seating plane c h 3 2 1 24 b 12 1 3 13 a plane gauge 0.05 min 0.15 max 0-8 0.60 0.15 0.90 1.00 ref 0.25 see detail "x" 0.15 0.25 (0.65 typ) (5.65) (0.35 typ) (1.45) 6.40 4.40 0.10 0.65 1.20 max pin #1 i.d. mark 7.80 0.10 +0.05 -0.06 -0.06 +0.05 -0.10 +0.15 0.20 c b a 0.10 c - 0.05 0.10 c b a m |
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